1. Field of the Invention
The present invention relates to a method and apparatus for performing a probing test for electrically testing chips such as ICs formed in a semiconductor wafer and, more particularly, to a method and apparatus for properly testing a chip of interest with high efficiency.
2. Description of the Related Art
Semiconductor devices such as ICs and LSIs must be tested during the manufacturing process several times so as to evaluate their electrical characteristics. A wafer test process is performed between a wafer forming process and an assembly process. That is, the wafer test process is performed in units of device patterns after preprocesses such as pattern etching and protective film coating.
A wafer test system basically includes a wafer probing machine (also called a wafer prober) and a tester. These components are connected via a measuring line. A test complete signal and a test fail signal are exchanged between the wafer probing machine and the tester in response to a test start signal on a test control line.
This wafer probing machine comprises an X-Y table movable along the X- and Y-axes, a wafer-setting stage equipped on the X-Y table, and a probe card having a large number of probes which are brought into contact with electrodes of each chip in the semiconductor wafer placed on the wafer-setting stage.
In a probing test, when a test of a given chip is completed, the wafer-setting stage is moved in the Z-axes, the X-Y table is moved in the X- and Y-axes, and the next chip is tested. In this manner, a large number of chips arranged on the wafer in a matrix form are tested in units of rows. Chips which are discriminated as defective chips are marked with an ink or the like.
As shown in FIG. 1, a large number of chips 3 are arranged in semiconductor wafer 1 in a matrix form. In the matrix of chips 3, a direction parallel to orientation flat 1a of wafer 1 defines "rows", and a direction perpendicular to orientation flat 1a defines "columns". Since wafer 1 is almost circular, omissions occur in chips 2 in the peripheral area of the wafer, and these chips are detected as defective chips. For this reason, chips 2 in the peripheral area of the wafer are eliminated from chips subjected to the test from the beginning, and a test time is shortened.
An edge-correction method is used as a conventional means for eliminating defective chips 2 in the peripheral area of the wafer from chips subjected to the test.
According to the edge-correction method, when a total area of each chip 3 to be formed in semiconductor wafer 1 is given as 100%, a numeric value is preset as a parameter for determining a percentage of chip area subjected to the test to determine whether a chip of interest is excluded from chips subjected to the test on the basis of the above numeric value.
Assume that a parameter value of edge-correction is set to be 50%. In this case, when the area of a chip in the peripheral area of the wafer is less than 50% of the total area of nondefective chip 3, this peripheral chip is excluded from chips subjected to the test.
A calculation technique of edge-correction will be described below.
When a semiconductor wafer is placed on a wafer carrier in a probing test machine and is positioned thereon, the diameter and central position of the wafer are measured. An edge-correction value of each chip is calculated on the basis of the measured values.
As shown in FIG. 2, central point O of semiconductor wafer 1 is given as an origin, and X-Y coordinates (a,c), (a,d), (b,d), and (b,c) of four corner points A, B, C, and D are measured. Distances between central point O and four points A, B, C, and D are calculated. The calculated distances are compared with radius R of the semiconductor wafer to determine whether each chip is perfectly formed on wafer 1. For example, for chip 2 in FIG. 2:
______________________________________ R.sup.2 &gt; a.sup.2 + c.sup.2 Point A: on wafer R.sup.2 &gt; a.sup.2 + d.sup.2 Point B: on wafer R.sup.2 &lt; b.sup.2 + d.sup.2 Point C: off wafer R.sup.2 &lt; b.sup.2 + c.sup.2 Point D: off wafer ______________________________________
and this chip 2 is determined to be located in the peripheral portion of wafer 1 and to be a chip with an omission.
However, for chip 3 in FIG. 2:
______________________________________ R.sup.2 &gt; a.sup.2 + c.sup.2 Point A: on wafer R.sup.2 &gt; a.sup.2 + d.sup.2 Point B: on wafer R.sup.2 &gt; b.sup.2 + d.sup.2 Point C: on wafer R.sup.2 &gt; b.sup.2 + c.sup.2 Point D: on wafer ______________________________________
and this chip 3 is determined to be a nondefective chip without any omission.
When above-mentioned chip 2 is determined to be a chip with an omission, the area of chip 2 is calculated and compared with the area of nondefective chip 3 to obtain an area ratio. The calculated area ratio is compared with the preset edge-correction parameter value to determine whether chip 2 can be a chip subjected to the test or not.
Conventional probing test procedures will be described below.
The wafer carrier is moved such that the leftmost chip in the uppermost row of chips satisfies a preset-edge-correction-condition, which is located at a chip measurement portion. The leftmost chip is measured. It is then checked if the chip immediately to the right of the measured chip satisfies the preset-edge-correction-condition. If the condition is determined to be satisfied, the wafer carrier is moved, and this second chip is measured. However, if the condition is determined not to be satisfied, the wafer carrier is moved to a position where the rightmost chip of the next lower row of chips which satisfy the preset-edge-correction-condition is located to the measurement position. This rightmost chip is then measured The above operations are repeated. When there is no chip on semiconductor wafer 1 which satisfies the preset edge-correction condition, the measurement of this wafer is completed.
However, in a probing machine using the above edge-correction technique, a defective chip having almost the same area as that represented by the preset edge-correction condition is undesirably measured as a nondefective chip due to mechanical errors of the machine and measurement errors during positioning. Assume that the edge correction parameter value is given as 100%. A defective chip having an area ratio of about 98% may be undesirably measured. In addition, when defective chips are marked with an ink, some chips each having an area ratio of almost 100% are detected as nondefective chips and not marked with an ink. However, they are always judged as defective chips in subsequent visual checking, thereby adversely affecting the subsequent processes.
In addition, a dummy chip, e.g., a monitoring chip, is also measured. The measuring time per semiconductor wafer is prolonged, and the service life of measuring probes is shortened since unnecessary measurements i.e., measurements of several ten thousands of wafers per day are performed.
In order to solve the above problems, a so-called "probe-area-selection technique" is proposed. According to this technique, as shown in FIG. 3, distances between central point O of semiconductor wafer 1 and chips 4 located in wafer peripheral portions at angles of 0.degree., 90.degree., 180.degree., and 270.degree. are measured, and testing is performed by excluding chips 4 from the beginning.
Even if the probe area selection technique is employed, the edge-correction technique must also be employed in the following case. Chips 5 located in the wafer peripheral portions at angles of 45.degree., 135.degree., 225.degree., and 315.degree. (except 0.degree., 90.degree., 180.degree., 270.degree. ) from central point "O" are excluded from the range covered by the probe area selection technique and must be determined by the edge-correction technique. For this reason, a drawback inherent to the edge-correction technique is left unsolved even if the probe area selection technique is employed. Therefore, the above problems cannot be drastically solved.